Conventional processors may include multiple cores. For instance, a central processing unit (CPU) may include multiple ARM™ processing cores, where as a graphics processing unit (GPU) may include multiple shader cores. During operation of a multi-core processor, some cores may be active, whereas other cores may be inactive. Examples of a core being inactive include a core being clock-gated or power-collapsed or otherwise in an idle state. As load increases, the processor may increase the number of active cores, and as load decreases the processor may make some of the cores inactive.
Some processing jobs may be periodic in that they tend to use a relatively large amount of power at regular time intervals. Examples include graphics processing jobs handling a sequence of frames. When a large number of cores are active, it is a possibility that periodic processing by different cores may overlap, using a large amount of power and thereby causing voltage droops. The chance of voltage droops increases with an increasing number of active cores. Some voltage droops are harmless, though it may be undesirable for voltage to droop below a certain minimum level.
Furthermore, it is generally expected that voltage droop associated with a large number of cores may be larger than voltage droop associated with a small number of cores. Or put another way, as the number of active cores increases, possible voltage droops scenarios include potentially larger droops. Thus, conventional systems may build in a voltage margin so that the voltage is high enough during operation that expected droops will not lower the voltage below the baseline needed for the device to work. Also, such conventional systems would typically use a built-in voltage margin to withstand a worst-case scenario. Thus, in a processor having four cores, the conventional system would build a margin to accommodate four cores, and the processor would operate at that margin regardless of the number of cores that are active or inactive. However, this can be wasteful, as higher operating voltages may be expected to increase leakage current in the transistors of the processor. There is, therefore, a desire in the art for better techniques to provide adequate voltage margin.